SM320C6414-EP_16 Datasheet, PDF (55/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5.1.4 Timing Requirements ECLKIN for EMIFA and EMIFB ^{(1) (2) (3)} (see Figure 5-8)
NO.
PARAMETER
–50xEP
MIN
MAX
UNIT
1
t_c(EKI)
Cycle time, ECLKIN
6 ⁽⁴⁾
16P
ns
2
t_w(EKIH)
Pulse duration, ECLKIN high
2.7
ns
3
t_w(EKIL)
Pulse duration, ECLKIN low
2.7
ns
4
t_t(EKI)
Transition time, ECLKIN
2
ns
5
t_J(EKI)
Peak-to-Peak jitter, ECLKIN
0.02E
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
(2) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.
(3) These C64xE devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an A and all EMIFB signals
are prefixed by a B. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix A or B may be omitted.
(4) Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to ac timing
requirements. On the 7E3 and 6E3 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are
met. On the 5E0 devices, 100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
5
1
4
2
ECLKIN
3
4
Figure 5-8. ECLKIN Timing for EMIFA and EMIFB
NO.
PARAMETER
–50xEP
MIN
MAX
1
t_J(EKO1)
Cycle-to-cycle jitter, ECLKOUT1
0
±175 ⁽¹⁾
2
t_w(EKO1H)
Pulse duration, ECLKOUT1 high
ER – 0.7 EH + 0.7
3
t_w(EKO1L)
Pulse duration, ECLKOUT1 low
EL – 0.7 EL + 0.7
4
t_t(EKO1)
Transition time, ECLKOUT1
1
5 t_{d(EKIH-EKO1H)} Delay time, ECLKIN high to ECLKOUT1 high
1
8
6 t_{d(EKIL-EKO1L)} Delay time, ECLKIN low to ECLKOUT1 low
1
8
(1) This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
UNIT
ns
ns
ns
ns
ns
ns
ECLKIN
ECLKOUT1
1
5
6
3
2
4
4
Figure 5-9. ECLKOUT1 Timing for EMIFA and EMIFB Modules
NO.
PARAMETER
–50xEP
MIN
MAX
1
t_J(EKO2)
Cycle-to-cycle jitter, ECLKOUT2
0
±175 ⁽¹⁾
2
t_w(EKO2H)
Pulse duration, ECLKOUT2 high
05NE – 0.7 05NE + 0.7
3
t_w(EKO2L)
Pulse duration, ECLKOUT2 low
05NE – 0.7 05NE + 0.7
4
t_t(EKO2)
Transition time, ECLKOUT2
1
5
t_{d(EKIH-EKO2H)} Delay time, ECLKIN high to ECLKOUT2 high
1
8
6
t_{d(EKIL-EKO2L)} Delay time, ECLKIN low to ECLKOUT2 low
1
8
(1) This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
UNIT
ns
ns
ns
ns
ns
ns
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PARAMETER MEASUREMENT INFORMATION
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