SM320C6414-EP_16 Datasheet, PDF (82/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
1
2
3
3
4
4
5
6
7
2
3
3
Bit(n-1)
9
8
(n-2)
11
10
12
Bit 0
14
13
Bit(n-1)
13
(n-2)
Figure 5-40. McBSP Timing
(n-3)
(n-3)
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5.12.3 Timing Requirements for FSR When GSYNC = 1 (see Figure 5-41)
NO.
PARAMETER
1
t_su(FRH-CKSH)
2
t_h(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
1
2
Figure 5-41. FSR Timing When GSYNC = 1
–50xEP
MIN MAX
4
4
UNIT
ns
ns
5.12.4 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾
(2) _{(see )}
NO.
4 t_su(DRV-CKXL) Setup time, DR valid before CLKX low
–50xEP
MASTER
SLAVE
MIN MAX
MIN MAX
12
2 – 12P
UNIT
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
82
PARAMETER MEASUREMENT INFORMATION
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