SM320C6414-EP_16 Datasheet, PDF (70/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
AECLKOUT1
≥ TRAS cycles
Self Refresh
ACEx
ABE[7:0]
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End Self-Refresh
AEA[22:14, 12:3]
AEA13
AED[63:0]
AAOE/ASDRAS/ASOE^‡
AARE/ASDCAS/ASADS/
ASRE^‡
AAWE/ASDWE/ASWE^‡
13
13
ASDCKE
A. These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an A and all EMIFB
signals are prefixed by a B. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix A or
B may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic (SDCAS, SDWE, and
SDRAS) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for
EMIFB)].
B. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,
and ASDRAS, respectively, during SDRAM accesses.
Figure 5-23. SDRAM Self-Refresh Timing for EMIFA Only
5.5 HOLD/HOLDA TIMING
5.5.1 Timing Requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB Modules
(1)_{(see Figure 5-24)}
NO.
PARAMETER
3
t_{oh(HOLDAL-HOLDL)} Hold time, HOLD low after HOLDA low
(1) E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
–50xEP
MIN MAX
E
UNIT
ns
70
PARAMETER MEASUREMENT INFORMATION
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