SM320C6414-EP_16 Datasheet, PDF (80/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
PCLK
1
2
PCI Output
3
PCI Input
Valid
4
Valid
5
6
Figure 5-38. PCI Input/Output Timing
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5.11.5 Timing Requirements for Serial EEPROM Interface (see Figure 5-39)
NO.
8
t_su(DIV-CLKH)
9
t_h(CLKH-DIV)
Setup time, XSP_DI valid before XSP_CLK high
Hold time, XSP_DI valid after XSP_CLK high
–50xEP
MIN MAX
50
0
UNIT
ns
ns
NO.
1
t_w(CSL)
Pulse duration, XSP_CS low
2
t_d(CLKL-CSL)
Delay time, XSP_CLK low to XSP_CS low
3
t_d(CSH-CLKH)
Delay time, XSP_CS high to XSP_CLK high
4
t_w(CLKH)
Pulse duration, XSP_CLK high
5
t_w(CLKL)
Pulse duration, XSP_CLK low
6 t_{osu(DOV-CLKH)} Output setup time, XSP_DO valid after XSP_CLK high
7 t_oh(CLKH-DOV) Output hold time, XSP_DO valid after XSP_CLK high
–50xEP
MIN TYP
4092P
0
2046P
2046P
2046P
2046P
2046P
MAX
UNIT
ns
ns
ns
ns
ns
XSP_CS
3
4
5
XSP_CLK
XSP_DO
XSP_DI
6
7
9
8
2
1
Figure 5-39. PCI Serial EEPROM Interface Timing
5.12 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
80
PARAMETER MEASUREMENT INFORMATION
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