SM320C6414-EP_16 Datasheet, PDF (29/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
3 Development Support ................................. 43
3.1 Device and Development Support Tool
Nomenclature ....................................... 43
4 Electrical Specifications .............................. 50
4.1 ABSOLUTE MAXIMUM RATINGS .................. 50
4.2 RECOMMENDED OPERATING CONDITIONS .... 50
4.3 ELECTRICAL CHARACTERISTICS ................ 50
5 PARAMETER MEASUREMENT INFORMATION .. 52
5.1 Signal Transition Levels............................. 52
5.2 Signal Transition Rates ............................. 52
5.3 Timing Parameters and Board Routing Analysis.... 52
5.1 INPUT AND OUTPUT CLOCKS .................... 53
5.1.1 Timing Requirements for CLKIN for –50xEP
Devices (see Figure 5-5) ............................ 53
5.1.4 Timing Requirements ECLKIN for EMIFA and
EMIFB (see Figure 5-8) ............................. 55
5.2 ASYNCHRONOUS MEMORY TIMING ............. 56
5.2.1 Timing Requirements for Asynchronous Memory
Cycles for EMIFA Module (see Figure 5-11 and
Figure 5-12) ......................................... 56
5.2.3 Timing Requirements for Asynchronous Memory
Cycles for EMIFB Module (see Figure 5-11 and
Figure 5-12) ......................................... 56
5.3 PROGRAMMABLE SYNCHRONOUS INTERFACE
TIMING .............................................. 58
5.3.1 Timing Requirements for Programmable
Synchronous Interface Cycles for EMIFA Module
(see Figure 5-13) .................................... 58
5.3.3 Timing Requirements for Programmable
Synchronous Interface Cycles for EMIFB Module
(see Figure 5-13) ................................... 59
5.4 SYNCHRONOUS DRAM TIMING................... 62
5.4.1 Timing Requirements for Synchronous DRAM
Cycles for EMIFA Module (see Figure 5-16 ........ 62
5.4.3 Timing Requirements for Synchronous DRAM
Cycles for EMIFB Module(see Figure 5-16)......... 63
5.5 HOLD/HOLDA TIMING.............................. 70
5.5.1 Timing Requirements for the HOLD/HOLDA cycles
for EMIFA and EMIFB Modules (see Figure 5-24) . 70
5.6 Switching Characteristics Over Recommended
Operating Conditions for the HOLD/HOLDA Cycles
for EMIFA and EMIFB Modules (see Figure 5-24).. 71
5.7 BUSREQ TIMING ................................... 71
5.8 RESET TIMING ..................................... 72
5.8.1 Timing Requirements for Reset (see Figure 5-26 ) 72
5.9 EXTERNAL INTERRUPT TIMING .................. 74
5.9.1 Timing Requirements for External Interrupts (see
Figure 5-27) ......................................... 74
5.10 HOST-PORT INTERFACE (HPI).................... 74
5.10.1 Timing Requirements for Host-Port Interface
Cycles (see Figure 5-28 through Figure 5-35) ..... 74
5.11 PERIPHERAL COMPONENT INTERCONNECT
(PCI) TIMING (C6415 AND C6416 ONLY) ......... 78
5.11.1 Timing Requirements for PCLK (see Figure 5-36 79
5.11.2 Timing Requirements for PCI Reset (see
Figure 5-37) ......................................... 79
5.11.3 Timing Requirements for PCI Inputs (see
Figure 5-38) ......................................... 79
5.11.5 Timing Requirements for Serial EEPROM
Interface (see Figure 5-39).......................... 80
5.12 MULTICHANNEL BUFFERED SERIAL PORT
(McBSP) TIMING.................................... 80
5.12.1 Timing Requirements for McBSP (see
Figure 5-40 .......................................... 81
5.12.3 Timing Requirements for FSR When GSYNC = 1
(see Figure 5-41) .................................... 82
5.12.4 Timing Requirements for McBSP as SPI Master or
Slave: CLKSTP = 10b, CLKXP = 0 (see ) .......... 82
5.12.6 Timing Requirements for McBSP as SPI Master
or Slave: CLKSTP = 11b,
CLKXP = 1 (see Figure 5-43) ....................... 84
5.13 UTOPIA SLAVE TIMING (C6415 AND C6416
ONLY) ............................................... 84
5.13.1 Timing Requirements for UXCLK (see
Figure 5-44) ......................................... 85
5.13.2 Timing Requirements for URCLK (see Figure 5-45
...................................................... 85
5.13.3 Timing Requirements for UTOPIA Slave Transmit
(see Figure 5-46) .................................... 85
5.13.5 Timing Requirements for UTOPIA Slave Receive
(see Figure 5-47) .................................... 86
5.14 TIMER TIMING...................................... 87
5.14.1 Timing Requirements for Timer Inputs (see
Figure 5-48) ......................................... 87
5.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
PORT TIMING....................................... 87
5.15.1 Timing Requirements for GPIO Inputs (see
Figure 5-48) ......................................... 88
5.16 JTAG TEST PORT TIMING ......................... 88
5.16.1 Timing Requirements for JTAG Test Port (see
Figure 5-50) ......................................... 88
5.16.3 Thermal Resistance Characteristics (S-PBGA
Package) ............................................ 88
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