SM320C6414-EP_16 Datasheet, PDF (84/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
5.12.6 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b,
CLKXP = 1^{(1) (2)}(see Figure 5-43)
NO.
–50xEP
MASTER
SLAVE
MIN MAX
MIN MAX
4
t_su(DRV-CKXH)
5
t_h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
12
2 – 12P
4
5 + 24P
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
UNIT
ns
ns
NO.
PARAMETER
1 t_h(CKXH-FXL) Hold time, FSX low after CLKX low⁽⁴⁾
2 t_d(FXL-CKXXL) Delay time, FSX low to CLKX high⁽⁵⁾
3 t_d(CKXL-DXV) Delay time, CLKX low to DX valid
6 t_{dis(CKXH-DXHZ)} Disable time, DX high impedance following last data bit from
CLKX low
7
t_d(FXL-DXV)
Delay time, FSX low to DX valid
–50xEP
MASTER⁽³⁾
SLAVE
MIN MAX
MIN
MAX
H–2 H+3
T–2 T+1
–2
4 12P + 4 20P + 17
–2
4 12P + 3 20P + 17
UNIT
ns
ns
ns
ns
L–2 L–4
8P + 2 16P + 17 ns
(3) S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) × S
H = CLKX high pulse
width
= (CLKGDV/2 + 1) × S if CLKGDV is even
= (CLKGDV + 1)/2 × S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) × S if CLKGDV is even
= (CLKGDV + 1)/2 × S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave,
the active-low signal input on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSPF
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at
the rising edge of the Master clock (CLKX).
CLKX
FSX
DX
1
7
6
Bit 0
DR
Bit 0
2
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 5-43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
5.13 UTOPIA SLAVE TIMING (C6415 AND C6416 ONLY)
84
PARAMETER MEASUREMENT INFORMATION
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