SM320C6414-EP_16 Datasheet, PDF (73/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

www.ti.com
CLKOUT4
CLKOUT6
RESET
PCLK
ECLKIN
ECLKOUT1
ECLKOUT2
EMIF Z Group^‡§
EMIF High Group^‡
EMIF Low Group^‡
Low Group^‡
SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
Z Group^‡§
Boot and Device
Configuration Inputs^§¶
15
16
17
A. These C64x. devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an A and all EMIFB
signals are prefixed by a B. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix A or
B may be omitted [e.g., ECLKIN, ECLKOUT1, and ECLKOUT2].
B. The following groups consist of:
a. EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0],
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.
b. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)
c. EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding
HOLD input is low)
d. Low group consists of: XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI
EEPROM (BEA13) is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and
DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device
Configurations section of this data sheet.
e. Z group consists of : HD[310]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0,
FSX1/UXADDR3, FSX2, DX0, DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0,
FSR1/UXADDR2, FSR2, TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1,
PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR,
HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC,
UXCLAV, and URCLAV.
C. If BEA[20:13, 11, 7] and HD5/AD5 pins are actively driven, car must be taken to ensure no timing contention between
parameters 6, 7, 14, 15, 16, and 17.
D. Boot and Device Configurations Inputs (during reset) includ: EMIFB address pins BEA[20:13, 11, 7] and HD5/AD5.
The CI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.
Figure 5-26. Reset Timing^(A)
Submit Documentation Feedback
PARAMETER MEASUREMENT INFORMATION
73