SM320C6414-EP_16 Datasheet, PDF (71/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5.6 Switching Characteristics Over Recommended Operating Conditions for the
HOLD/HOLDA Cycles for EMIFA and EMIFB Modules ^{(1) (2) (3)} (see Figure 5-24)
NO.
PARAMETER
–50xEP
UNIT
MIN
MAX
1
t_{d(HOLDL-EMHZ)}
Delay time, HOLD low to EMIF Bus high impedance
2E
See ⁽⁴⁾
ns
2 t_{d(EMHZ-HOLDAL)} Delay time, EMIF Bus high impedance to HOLDA low
0
2E ns
4
t_{d(HOLDH-EMLZ)}
Delay time, HOLD high to EMIF Bus low impedance
2E
7E ns
5 t_{d(EMLZ-HOLDAH)} Delay time, EMIF Bus low impedance to HOLDA high
6 t_{d(HOLDL-EKOHZ)} Delay time, HOLD low to ECLKOUTx high impedance
0
2E ns
2E
See ⁽⁴⁾
ns
7 t_{d(HOLDH-EKOLZ)} Delay time, HOLD high to ECLKOUTx low impedance
2E
7E ns
(1) E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB
(2) For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE,
and AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE,
and BAWE/BSDWE/BSWE, BSOE3, and BPDT.
(3) The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ =
0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in
Figure 5-24.
(4) All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
3
HOLD
2
5
HOLDA
EMIF Bus^†
1
C64x
4
C64x
ECLKOUTx
6
7
ECLKOUTx
A. For EMIFA, EMIF Bus consists of : ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
and
AAWE/ASDWE/ASWE,
ASDCKE,
ASOE3,
and
APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE,
BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT.
Figure 5-24. HOLD/HOLDA Timing for EMIFA and EMIFB
5.7 BUSREQ TIMING
NO.
1
t_{d(AEKO1H-ABUSRV)}
2
t_{d(BEKO1H-BBUSRV)}
PARAMETER
Delay time, AECLKOUT1 high to ABUSREQ validA
Delay time, BECLKOUT1 high to BBUSREQ validB
–50xEP
MIN MAX
0.6
7.1
0.5
6.9
UNIT
ns
ns
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PARAMETER MEASUREMENT INFORMATION
71