SM320C6414-EP_16 Datasheet, PDF (41/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
TERMINAL
NAME
NO.
TYPE ⁽¹⁾
IPD/IPU
(2)
DESCRIPTION
BBE1
BBE0
D13 O/Z
C13 O/Z
IPU EMIFB byte–enable control
• Decoded from the low–order address bits. The number of address bits or byte enables
used depends on the width of external memory.
IPU _{• Byte–write enables for most types of memory}
• Can be directly connected to SDRAM read and write mask signal (SDQM)
BPDT
E12 O/Z
IPU EMIFB peripheral data transfer, allows direct transfer between external peripherals
EMIFB (16-Bit) — Bus Arbitration
BHOLDA
E13
O
IPU EMIFB hold–request–acknowledge to the host
BHOLD
B19
I
IPU EMIFB hold request from the host
BBUSREQ
E14
O
IPU EMIFB bus request output
EMIFB (16-Bit) — Asynchronous/Synchronous Memory Control
BECLKIN
A11
I
EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6
IPD clock) is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.
BECLKIN is the default for the EMIFB input clock.
BECLKOUT2
D11 O/Z
IPD
EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided by 1, 2, or 4.
BECLKOUT1
D12 O/Z
IPD
EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
BARE/BSDCAS/
BSADS/BSRE
A10
O/Z
EMIFB asynchronous memory read–enable/SDRAM column–address strobe/programmable
synchronous interface–address strobe or read–enable
IPU ^{• For programmable synchronous interface, the RENEN field in the CE Space ‘}
Secondary Control Register (CExSEC) selects between BSADS and BSRE: If RENEN
= 0, then the BSADS/BSRE signal functions as the BSADS signal. If RENEN = 1, then
the BSADS/BSRE signal functions as the BSRE signal.
BAOE/BSDRAS/
BSOE
B11
O/Z
IPU
EMIFB asynchronous memory output–enable/SDRAM row–address strobe/programmable
synchronous interface output–enable
BAWE/BSDWE/
BSWE
C11
O/Z
IPU
EMIFB asynchronous memory write–enable/SDRAM write–enable/programmable
synchronous interface write–enable
BSOE3
E15 O/Z
IPU EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)
BARDY
E11
I
IPU EMIFB asynchronous memory ready input
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Device Configurations
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