SM320C6414-EP_16 Datasheet, PDF (48/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
For maximum reliability, the TMS320C6414/15/16 DSP includes an internal pulldown (IPD) on the TRST
pin to ensure that TRST is always be asserted upon power up and the DSP internal emulation logic is
always properly initialized.
JTAG controllers from TI actively drive TRST high. However, some third-party JTAG controllers may not
drive TRST high, but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after power up and externally
drive TRST high before attempting any emulation or boundary-scan operations. Following the release of
RESET, the low-to-high transition of TRST must be seen to latch the state of EMU1 and EMU0. The
EMU[1:0] pins configure the device for either boundary scan mode or emulation mode. For more detailed
information, see the terminal functions section of this data sheet.
3.1.7 EMIF Device Speed
The rated EMIF speed (referring to both EMIFA and EMIFB) of these devices only applies to the SDRAM
interface when in a system that meets the following requirements:
• One bank (maximum of 2 chips) of SDRAM connected to EMIF
• Up to one bank of buffers connected to EMIF
• EMIF trace lengths between 1 inch and 3 inches
• 183-MHz SDRAM for 133-MHz operation (applies only to EMIFA)
• 143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all ac timings are met.
Verification of ac timings is mandatory when using configurations other than those specified. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all ac timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS
Models for Timing Analysis application report (SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines
(see the Terminal Functions table for the EMIF output signals).
3.1.8 Boot Mode
The C6414/15/16 device resets using the active-low signal RESET. While RESET is low, the device is
held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing
characteristics and states of device pins during reset. The release of RESET starts the processor running
with the prescribed device configuration and boot mode.
The C6414/C6415/C6416 has three types of boot modes:
• Host boot
If host boot is selected, upon release of RESET, the CPU is internally "stalled", while the remainder of
the device is released. During this period, an external host can initialize the CPU memory space as
necessary through the host interface, including internal configuration registers, such as those that
control the EMIF or other peripherals. For the C6414 device, the HPI peripheral is used for host boot.
For the C6415/C6416 device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI
peripheral is used for host boot if PCI_EN = 1. Once the host is finished with all necessary initialization,
it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes
the boot configuration logic to bring the CPU out of the "stalled" state. The CPU then begins execution
from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is
still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if the host boot
process is selected. All memory may be written to and read by the host. This allows for the host to
verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the CPU needs to
clear the DSPINT, otherwise, no more DSPINTs can be received.
• EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to
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