SM320C6414-EP_16 Datasheet, PDF (62/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
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ECLKOUTx
CEx
ABE[7:0] or BBE[1:0]
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
ARE/SDCAS/SADS/SRE^¶
Write
Latency =
1^‡
1
1
2
BE1
4
EA1
10
8
BE2
EA2
10
Q1
BE3
EA3
Q2
3
BE4
5
EA4
11
Q3
Q4
8
AOE/SDRAS/SOE^¶
12
12
AWE/SDWE/SWE^¶
A. These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an A and all EMIFB
signals are prefixed by a B. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix A or
B may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE,
SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for
EMIFB)].
B. The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields,
respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT
= 0.
C. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
a. Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency.
b. Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
c. CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final
command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is
active (CEEXT = 1).
d. Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with
deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN =
1).
e. Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
D. ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE,
respectively, during programmable synchronous interface accesses.
Figure 5-15. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write
Latency = 1) See Notes A, B, C)
5.4 SYNCHRONOUS DRAM TIMING
5.4.1 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see
Figure 5-16
NO.
PARAMETER
6
t_{su(EDV-EKO1H)} Setup time, read EDx valid before ECLKOUT1 high
7
t_h(EKO1H-EDV) Hold time, read EDx valid after ECLKOUT1 high
–50xEP
MIN MAX
2.1
2.5
UNIT
ns
ns
62
PARAMETER MEASUREMENT INFORMATION
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