SM320C6414-EP_16 Datasheet, PDF (81/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5.12.1 Timing Requirements for McBSP ^{(1) (2)} (see Figure 5-40
NO.
2
t_c(CKRX)
Cycle time, CLKR/X
3
t_w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
5 t_su(FRH-CKRL) Setup time, external FSR high before CLKR low
6 t_h(CKRL-FRH) Hold time, external FSR high after CLKR low
7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
8 t_h(CKRL-DRV) Hold time, DR valid after CLKR low
10 t_su(FXH-CKXL) Setup time, external FSX high before CLKX low
11 t_h(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
–50xEP
MIN
6.67 ⁽³⁾
0.5t_c(CKRX) - 1⁽³⁾
9
1.3
6
3
8
0.9
3
3.1
9
1.3
6
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and ac timing requirements.
NO.
PARAMETER
–50xEP
UNIT
MIN
MAX
1 t_{d(CKSH-CKRXH)} Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input
2
t_c(CKRX)
3
tw(CKRX)
4
t_d(CKRH-FRV)
9
t_d(CKXH-FXV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
CLKR/X int
CLKR/X int
CLKR int
CLKR int
CLKR ext
1.4
6.67 ⁽¹⁾
C – 1⁽⁴⁾
–2.1
–1.7
1.7
10 ns
ns
C + 1⁽⁴⁾ ns
3 ns
3 ns
9
12 t_{dis(CKXH-DXHZ)} Disable time, DX high impedance following last data bit from
CLKX high
CLKR int
CLKR ext
–3.9
4 ns
–2.1
9
13 t_d(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKR int
–3.9 + D1⁽⁵⁾ 4 + D2⁽⁵⁾ ns
CLKR ext –2.1 + D1⁽⁵⁾ 9 + D2⁽⁵⁾
14 t_d(FXH-DXV)H
Delay time, FSX high to DX valid
FSX int
ONLY applies when in data delay 0 (XDATDLY = 00b) moded _{FSX ext}
–2.3
5.6 ns
1.9
9
(1) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and ac timing requirements.
(4) C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) × S if CLKGDV is even
= (CLKGDV + 1)/2 × S if CLKGDV is odd or zero
L CLKX low pulse width = (CLKGDV/2) × S if CLKGDV is even
= (CLKGDV + 1)/2 × S if CLKGDV is odd or zero
(5) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
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PARAMETER MEASUREMENT INFORMATION
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