SM320C6414-EP_16 Datasheet, PDF (16/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
HEX ADDRESS
019C 0000
019C 0004
019C 0008
019C 000C–019C
01FF
ACRONYM
MUXH
MUXL
EXTPOL
–
Table 1-10. Interrupt Selector Registers
REGISTER NAME
Interrupt Multiplexer High
Interrupt Multiplexer Low
External Interrupt Polarity
COMMENTS
Selects which interrupts drive CPU interrupts 10–15
(INT10–INT15)
Selects which interrupts drive CPU interrupts 4–9
(INT04–INT09)
Sets the polarity of the external interrupts
(EXT_INT4–EXT_INT7)
Reserved
HEX ADDRESS
019C 0200
019C 0204–019F FFFF
Table 1-11. Peripheral Power-Down Control Register
ACRONYM
PDCTL
REGISTER NAME
Peripheral Power-Down Control
Reserved
HEX ADDRESS
018C 0000
0x3000 0000–0x33FF FFFF
018C 0004
0x3000 0000–0x33FF FFFF
018C 0008
018C 000C
018C 0010
018C 0014
018C 0018
018C 001C
018C 0020
018C 0024
018C 0028
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040–018F FFFF
Table 1-12. McBSP 0 Registers
ACRONYM
DRR0
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCERE00
XCERE00
PCR0
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
REGISTER NAME
COMMENTS
McBSP0 Data Receive Register via configuration bus
The CPU and EDMA controller
can only read this register; they
cannot write to it.
McBSP0 Data Receive Register via peripheral bus
McBSP0 Data Transmit Register via configuration bus
McBSP0 Data Transmit Register via peripheral bus
McBSP0 Serial Port Control Register
McBSP0 Receive Control Register
McBSP0 Transmit Control Register
McBSP0 Sample Rate Generator Register
McBSP0 Multichannel Control Register
McBSP0 Enhanced Receive Channel Enable Register 0
McBSP0 Enhanced Transmit Channel Enable Register
0
McBSP0 Pin Control Register
McBSP0 Enhanced Receive Channel Enable Register 1
McBSP0 Enhanced Transmit Channel Enable Register
1
McBSP0 Enhanced Receive Channel Enable Register 2
McBSP0 Enhanced Transmit Channel Enable Register
2
McBSP0 Enhanced Receive Channel Enable Register 3
McBSP0 Enhanced Transmit Channel Enable Register
3
Reserved
HEX ADDRESS
018C 0000
0x3400 0000–0x37FF
FFFF
019C 0004
ACRONYM
DRR1
Table 1-13. McBSP 1 Registers
REGISTER NAME
McBSP1 Data Receive Register via configuration bus
COMMENTS
The CPU and EDMA controller can
only read this register; they cannot
write to it.
DRR1
McBSP1 Data Receive Register via peripheral bus
DXR1
McBSP1 Data Transmit Register via configuration bus
16
Introduction
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