SM320C6414-EP_16 Datasheet, PDF (86/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
NO.
PARAMETER
6
t_{d(UXCH-UXCLAVHZ)}
Delay time, UXCLK high to UXCLAV Hi-Z
7
t_{w(UXCLAVL-UXCLAVHZ)} Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
10
t_d(UXCH-UXSV)
Delay time, UXCLK high to UXSOC valid
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–50xEP
MIN MAX
9 18.5
3
3
12
UNIT
ns
ns
ns
UXCLK
1
UXDATA[7:0]
P45
P46
P47
P48
H1
UXADDR[4:0]
0 x1F
N
UXCLAV
0x1F
N
3
2
N
0x1F
N+1
0x1F
6
7
4
5
N
9
8
UXENB
10
UXSOC
† The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC
signals).
(1) The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and
UXSOC signals).
Figure 5-46. UTOPIA Slave Transmit Timing⁽¹⁾
5.13.5 Timing Requirements for UTOPIA Slave Receive (see Figure 5-47)
NO.
1
2
3
4
9
10
11
12
NO.
t_{su(URDV-URCH)}
t_h(URCH-URDV)
t_{su(URAV-URCH)}
t_h(URCH-URAV)
t_{su(URENBL-URCH)}
t_{h(URCH-URENBL)}
t_{su(URSH-URCH)}
t_h(URCH-URSH)
Setup time, URDATA valid before URCLK highR
Hold time, URDATA valid after URCLK high
Setup time, URADDR valid before URCLK highR
Hold time, URADDR valid after URCLK high
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK highU
Hold time, URSOC high after URCLK high
PARAMETER
5
t_{d(URCH-URCLAV)}
Delay time, URCLK high to URCLAV driven active value
6
t_{d(URCH-URCLAVL)}
Delay time, URCLK high to URCLAV driven inactive low
7
t_{d(URCH-URCLAVHZ)}
Delay time, URCLK high to URCLAV Hi-Z
8
t_{w(URCLAVL-URCLAVHZ)} Pulse duration (low), URCLAV low to URCLAV Hi-Z
–50xEP
MIN
MAX
4
1
4
1
4
1
4
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
–50xEP
MIN MAX
3
12
3
12
9 18.5
3
UNIT
ns
ns
ns
ns
86
PARAMETER MEASUREMENT INFORMATION
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