SM320C6414-EP_16 Datasheet, PDF (85/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5.13.1 Timing Requirements for UXCLK⁽¹⁾ (see Figure 5-44)
NO.
1
t_c(UXCK)
Cycle time, UXCLK
2
t_w(UXCKH)
Pulse duration, UXCLK high
3
t_w(UXCKL)
Pulse duration, UXCLK low
4
t_t(UXCK)
Transition time, UXCLK
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
–50xEP
MIN
MAX
20
0.4t_c(UXCK)
0.4t_c(UXCK)
0.6t_c(UXCK)
0.6t_c(UXCK)
2
UNIT
ns
ns
ns
ns
1
4
2
UXCLK
3
4
Figure 5-44. UXCLK Timing
5.13.2 Timing Requirements for URCLK⁽¹⁾ (see Figure 5-45
NO.
1
t_c(URCK)
Cycle time, URCLK
2
t_w(URCKH)
Pulse duration, URCLK high
3
t_w(URCKL)
Pulse duration, URCLK low
4
t_t(URCK)
Transition time, URCLK
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
1
4
2
URCLK
3
Figure 5-45. URCLK Timing
–50xEP
MIN
MAX
20
0.4t_c(URCK)
0.4t_c(URCK)
0.6t_c(URCK)
0.6t_c(URCK)
2
UNIT
ns
ns
ns
ns
4
5.13.3 Timing Requirements for UTOPIA Slave Transmit (see Figure 5-46)
NO.
2
t_{su(UXAV-UXCH)}
Setup time, UXADDR valid before UXCLK high
3
t_h(UXCH-UXAV)
Hold time, UXADDR valid after UXCLK high
8
t_{su(UXENBL-UXCH)} Setup time, UXENB low before UXCLK high
9
t_{h(UXCH-UXENBL)} Hold time, UXENB low after UXCLK high
NO.
PARAMETER
1
t_d(UXCH-UXDV)
4
t_{d(UXCH-UXCLAV)}
5
t_{d(UXCH-UXCLAVL)}
Delay time, UXCLK high to UXDATA valid
Delay time, UXCLK high to UXCLAV driven active value
Delay time, UXCLK high to UXCLAV driven inactive low
–50xEP
MIN MAX
4
1
4
1
UNIT
ns
ns
ns
ns
–50xEP
MIN MAX
3
12
3
12
3
12
UNIT
ns
ns
ns
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PARAMETER MEASUREMENT INFORMATION
85