SM320C6414-EP_16 Datasheet, PDF (36/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
TERMINAL
NAME
NO.
TYPE ⁽¹⁾
IPD/IPU
(2)
DESCRIPTION
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
GP15/PRST ⁽⁶⁾
GP14/PCLK ⁽⁶⁾
GP13/PINTA ⁽⁶⁾
GP12/PGNT ⁽⁶⁾
GP11/PREQ ⁽⁶⁾
GP10/PCBE3 ⁽⁶⁾
GP9/PIDSEL ⁽⁶⁾
AF4
AD5
I/O/Z
AE5
AF5
G3
F2
G4
J3 I/O/Z
F1
L2
M3
General-purpose input/outputs (GPIO) (I/O/Z) or external interrupts (input only). The default
after reset setting is GPIO enabled as input only.
IPU When these pins function as external interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge driven and the polarity can be independently
selected via the External Interrupt Polarity Register bits (EXTPOL[3:0]).
General-purpose input/output (GPIO) 15 (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 (I/O/Z) or PCI clock (I). No function at default.
GPIO 13 (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 (I/O/Z) or PCI bus grant (I). No function at default.
GPIO 11 (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GPIO 9 (I/O/Z) or PCI initialization device select (I). No function at default.
GP3
AC6 I/O/Z
GPIO 3 (I/O/Z). The default after reset setting is GPIO 3 enabled as input only.
GP0
AF6 I/O/Z
IPD
GPIO 0 (I/O/Z). Can be programmed as GPIO 0 (input only) (default) or as GPIO 0 (output
only) pin or output as a general-purpose interrupt (GP0INT) signal (output only).
CLKS2/GP8^{(6) (7)}
CLKOUT6/GP2 ⁽⁶⁾
(7)
AE4
AD6
I/O/Z
I/O/Z
IPD
McBSP2 external clock source (CLKS2) [input only] (default) or this pin can be
programmed as a GPIO 8 pin (I/O/Z).
IPD
Clock output at 1/6 of the device speed (O/Z) (default) or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
CLKOUT4/GP1
(6) (7)
AE6 I/O/Z
IPD
Clock output at 1/4 of the device speed (O/Z) (default) or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
Host-Port Interface (HPI) (C64x) or Peripheral Component Interconnect (PCI) (C6415 or C6416 Devices Only)
PCI_EN
AA4
I
HINT/PFRAME⁽⁶⁾ R4 I/O/Z
PCI enable. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or PCI
peripherals (for the C6415 and C6416 devices). This pin works in conjunction with the
IPD
MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device
Configurations section of this data manual).
The C6414 device does not support the PCI peripheral; for proper device operation, do not
oppose the internal pulldown (IPD) on this pin.
Host interrupt from DSP to host (O) (default) or PCI frame (I/O/Z)
HCNTL1/PDEVS
EL ⁽⁶⁾
R1
HCNTL0/PSTOP ⁽
6)
T4
I/O/Z
I/O/Z
Host control 1. Selects between control, address, or data registers (I) (default) or PCI
device select (I/O/Z).
Host control 0. Selects between control, address, or data registers (I) (default) or PCI stop
(I/O/Z).
HHWIL/PTRDY⁽⁶⁾ R3
HR/W/PCBE2 ⁽⁶⁾
P1
HAS/PPAR ⁽⁶⁾
T3
HCS/PPERR ⁽⁶⁾
R2
HDS1/PSERR ⁽⁶⁾
T1
HDS2/PCBE1 ⁽⁶⁾
T2
HRDY/PIRDY ⁽⁶⁾
P4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host half-word select-first or second half word (not necessarily high or low order) (For
HPI16 bus width selection only) (I) (default) or PCI target ready (I/O/Z).
Host read or write select (I) (default) or PCI command/byte enable 2 (I/O/Z)
Host address strobe (I) (default) or PCI parity (I/O/Z)
Host chip select (I) (default) or PCI parity error (I/O/Z)
Host data strobe 1 (I) (default) or PCI system error (I/O/Z)
Host data strobe 2 (I) (default) or PCI command/byte enable 1 (I/O/Z)
Host ready from DSP to host (O) (default) or PCI initiator ready (I/O/Z)
(6) For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data
manual. The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are stand alone
peripheral functions for this device.
(7) For the C6414 device, only these pins are multiplexed pins.
36
Device Configurations
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