C8051F52X Datasheet, PDF (92/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt,
5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to exe-
cute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the
new interrupt will not be serviced until the current ISR completes, including the RETI and following instruc-
tion.
Table 11.1. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Enable
Flag
Priority
Control
Reset
0x0000
External Interrupt 0(/INT0)
Timer 0 Overflow
External Interrupt 1(/INT1)
Timer 1 Overflow
0x0003
0x000B
0x0013
0x001B
UART
0x0023
Timer 2 Overflow
0x002B
SPI0
0x0033
ADC0 Window
Comparator
ADC0 End of Conversion
Programmable Counter
Array
Comparator Falling Edge
0x003B
0x0043
0x004B
0x0053
Top None
N/A N/A
0 IE0 (TCON.1)
YY
1 TF0 (TCON.5)
YY
2 IE1 (TCON.3)
YY
3 TF1 (TCON.7)
YY
4
RI0 (SCON0.0)
TI0 (SCON0.1)
YN
5
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
YN
SPIF (SPI0CN.7)
6
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
YN
RXOVRN (SPI0CN.4)
7
AD0WINT
(ADC0CN.3)
YN
8 AD0INT (ADC0CN.5) Y N
9
CF (PCA0CN.7)
CCFn (PCA0CN.n)
YN
10 CP0FIF (CPT0CN.4) N N
Comparator Rising Edge 0x005B 11 CP0RIF (CPT0CN.5) N N
LIN Interrupt
0x0063 12 LININT (LINST.3)
N N*
Voltage Regulator Dropout 0x006B 13 N/A
N/A N/A
Port Match
0x0073 14 N/A
N/A N/A
*Note: To clear LININT requires the application to set the RSTINT bit (LINCTRL.3)
Always
Enabled
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES0 (IE.4)
ET2 (IE.5)
ESPI0
(IE.6)
EWADC0
(EIE1.0)
EADC0
(EIE1.1)
EPCA0
(EIE1.2)
ECPF
(EIE1.3)
ECPR
(EIE1.4)
ELIN
(EIE1.5)
EREG0
(EIE1.6)
EMAT
(EIE1.7)
Always
Highest
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
PS0 (IP.4)
PT2 (IP.5)
PSPI0
(IP.6)
PWADC0
(EIP1.0)
PADC0
(EIP1.1)
PPCA0
(EIP1.2)
PCPF
(EIP1.3)
PCPR
(EIP1.4)
PLIN
(EIP1.5)
PREG0
(EIP1.6)
PMAT
(EIP1.7)
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