C8051F52X Datasheet, PDF (35/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
RST/C2CK 1
P0.0/VREF 2
GND 3
VDD
4
VREGIN
5
C8051F530/1/3/4/6/7
Top View
GND
15 P0.6/C2D
14 P0.7/XTAL1
13 P1.0/XTAL2
12 P1.1
11 P1.2/CNVSTR
Table 4.3. Pin Definitions for the C8051F530 (QFN 20)
Name
RST/
Pin
Type Description
D I/O _{Device Reset. Open-drain output of internal POR or VDD monitor. An}
external source can initiate a system reset by driving this pin low for at
1
least 15 µs. A 1 kΩ pullup to V_DD is recommended. See Reset
Sources Section for a complete description.
C2CK
P0.0/
V_REF
GND
V_DD
V_REGIN
P1.7
P1.6
P1.5
D I/O _{Clock signal for the C2 Debug Interface.}
D I/O or _{Port 0.0. See Port I/O Section for a complete description.}
A In
2
A O or
D In
External V_REF Input. See V_REF Section.
3
Ground.
4
Core Supply Voltage.
5
On-Chip Voltage Regulator Input.
6
D I/O or _{Port 1.7. See Port I/O Section for a complete description.}
A In
7
D I/O or _{Port 1.6. See Port I/O Section for a complete description.}
A In
8
D I/O or _{Port 1.5. See Port I/O Section for a complete description.}
A In
*Note: Please refer to Section “21. Revision Specific Behavior” on page 215.
Rev. 0.3
35