C8051F52X Datasheet, PDF (141/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
15.3. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately fol-
lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ-
ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a
false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL bit in register CLKSEL selects which oscillator source is used as the system clock. CLKSL
must be set to ‘1’ for the system clock to run from the external oscillator; however the external oscillator
may still clock certain peripherals (timers, PCA) when another oscillator is selected as the system clock.
The system clock may be switched on-the-fly between the internal oscillator and external oscillator, as long
as the selected clock source is enabled and has settled.
SFR Definition 15.5. CLKSEL: Clock Select
R
R
R/W
R/W
R
R/W
R/W
R/W
Reset Value
-
-
Reserved Reserved
-
Reserved Reserved CLKSL 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA9
Bits7–6: Unused. Read = 00b; Write = don’t care.
Bits5–4: Reserved. Read = 0b; Must write 0b.
Bit3: Unused. Read = 0b; Write = don’t care.
Bits2–1: Reserved. Read = 0b; Must write 0b.
Bit0: CLKSL: System Clock Select
0: Internal Oscillator (as determined by the IFCN bits in register OSCICN).
1: External Oscillator.
Rev. 0.3
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