C8051F52X Datasheet, PDF (105/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 12.1. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
RST Output Low Voltage
Conditions
I_OL = 8.5 mA, V_DD = 2.1 V
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
RST = 0.0 V
V_DD Monitor Threshold (V_RST-LOW)
V_DD Monitor Threshold (V_RST-HIGH)
Missing Clock Detector Timeout
Time from last system
clock rising edge to reset
initiation
Reset Time Delay
Delay between release of
any reset source and
code execution at location
0x0000
Minimum RST Low Time to Generate a
System Reset
V_DD Monitor Turn-on Time
V_DD Monitor Supply Current
V_DD = 2.1 V
Min
—
0.7 x
V_DD
—
—
TBD
TBD
TBD
TBD
TBD
TBD
—
Typ Max Units
—
0.8
V
—
—
V
0.3 x
—
V_DD
V
14
TBD µA
1.7
TBD
V
2.2
TBD
V
350
650 µs
—
—
µs
—
—
µs
—
—
µs
23
TBD µA
Rev. 0.3
105