C8051F52X Datasheet, PDF(101/220 Page) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52X Datasheet, PDF (101/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52x-53x

12.2. Power-Fail Reset / VDD Monitor

When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply

monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 12.2). When VDD returns

to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data

memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below

the level required for data retention. If the PORSF flag reads â1â, the data may no longer be valid. The VDD

monitor is enabled and is not selected as a reset source after power-on resets; however its defined state

(enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is disabled by

software, and a software reset is performed, the VDD monitor will still be disabled after the reset. To pro-

tect the integrity of Flash contents, the VDD monitor must be enabled to the higher setting

(VDMLVL = '1') and selected as a reset source if software contains routines which erase or write

Flash memory. If the VDD monitor is not enabled, any erase or write performed on Flash memory

will cause a Flash Error device reset.

The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor

as a reset source before it is enabled and stabilized may cause a system reset. The procedure for re-

enabling the VDD monitor and configuring the VDD monitor as a reset source is shown below:

Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = â1â).

Step 2. Wait for the VDD monitor to stabilize (see Table 12.1 for the VDD Monitor turn-on time).

Note: This delay should be omitted if software contains routines which erase or

write Flash memory.

Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = â1â).

See Figure 12.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.

See Table 12.1 for complete electrical characteristics of the VDD monitor.

Note: Software should take care not to inadvertently disable the VDD Monitor as a reset source

when writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to

RSTSRC should explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset source.

Rev. 0.3

101

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