C8051F52X Datasheet, PDF (163/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
It is important to note that in all these equations the results must be rounded down to the nearest integer.
The following example calculates the factors for a Master node running at 24.5 MHz and communicating at
19.2 Kbits/sec. First, the multiplier will be calculated:
multiplier = ^{2----0---0---0---0-} – 1 = 0.0417 ≅ 0
19200
After this step the prescaler is calculated:
prescaler
=
l n ₍---0----+-----1---2-₎--4-_×--5---10---90---20---00---00-----_×----2---0---0--
× ---1---- – 1
ln2
=
1.674 ≅ 1
Then the divider is calculated:
divider
=
-------------------2---4---5---0---0---0---0---0--------------------
2^{(1 + 1)} × (0 + 1) × 19200
=
319.010 ≅ 319
These values will lead to the following bit_rate:
bit_rate
=
----------------2---4---5---0---0---0---0---0-----------------
2^{(1 + 1)} × (0 + 1) × 319
≅
19200.63
The following code fragment programs the interface in Master mode, using the Enhanced Checksum and
enabling the interface to operate at 9600 bits/sec from a system clock (SYSCLK) of 24.5 MHz.
LINCF = 0x80;
// Activate the interface
LINADDR = 0x09;// Point to the status register
LINCF |= 0x40;// Set the part as Master
LINADDR = 0x0D;// Point to the LINMUL register
// Initialize the register (prescaler, multiplier and bit 8 of divider)
LINDATA = (_0x01 << 6 ) + (_0x00 << 1 ) + ( (_0x13F & 0x0100 ) >> 8 );
LINADDR = 0x0C;// Point to the LINDIV register
LINDATA = (unsigned char)_0x13F;// Initialize LINDIV
LINADDR = 0x0B;// Point to the LINSIZE register
LINDATA |= 0x80;
// Initialize the checksum as Enhanced
LINADDR = LINCTRL;
// Point to LINCTRL register
LINDATA = RSTERR | RSTINT; // Reset any error and the interrupt
Table 17.3 presents some typical values of system clock and bit rate along with their factors:
Rev. 0.3
163