C8051F52X Datasheet, PDF (34/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 4.2. Pin Definitions for the C8051F530 (TSSOP 20) (Continued)
Name
P1.5
P1.4
P1.3
P1.2/
CNVSTR
P1.1
P1.0/
Pin
Type Description
10
D I/O or _{Port 1.5. See Port I/O Section for a complete description.}
A In
11
D I/O or _{Port 1.4. See Port I/O Section for a complete description.}
A In
12
D I/O or _{Port 1.3. See Port I/O Section for a complete description.}
A In
D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
13
D In _{External Converter start input for the ADC0, see Section “5. 12-Bit}
ADC (ADC0)” on page 41 for a complete description.
14
D I/O or _{Port 1.1. See Port I/O Section for a complete description.}
A In
D I/O or _{Port 1.0. See Port I/O Section for a complete description.}
A In
XTAL2
15
D I/O ^{External Clock Output. For an external crystal or resonator, this pin is}
the excitation driver. This pin is the external clock input for CMOS,
capacitor, or RC oscillator configurations. See Section “15. Oscillators”
on page 133.
P0.7/
XTAL1
P0.6/
D I/O or _{Port 0.7. See Port I/O Section for a complete description.}
A In
16
A In External Clock Input. This pin is the external oscillator return for a crys-
tal or resonator. Section “15. Oscillators” on page 133.
D I/O or _{Port 0.6. See Port I/O Section for a complete description.}
17
A In
C2D
P0.5/RX*
D I/O Bi-directional data signal for the C2 Debug Interface.
18
D I/O or _{Port 0.5. See Port I/O Section for a complete description.}
A In
P0.4/TX*
19
D I/O or _{Port 0.4. See Port I/O Section for a complete description.}
A In
P0.3
20
D I/O or _{Port 0.3. See Port I/O Section for a complete description.}
A In
*Note: Please refer to Section “21. Revision Specific Behavior” on page 215.
34
Rev. 0.3