C8051F52X Datasheet, PDF (122/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
P0
SF Signals QFN 10
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS**
LIN-TX
LIN-RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0 1 2 3 4* 5*
001100
P0SKIP[0:5]
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be manually configured
to skip their corresponding port pins.
*Note: Refer to Section “21. Revision Specific Behavior” on page 215.
**Note: 4-Wire SPI Only.
Figure 14.6. Crossbar Priority Decoder with Crystal Pins Skipped (QFN 10)
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.3 or
P0.4*; UART RX0 is always assigned to P0.4 or P0.5*. Standard Port I/Os appear contiguously starting at
P0.0 after prioritized functions and skipped pins are assigned.
*Note: Refer to Section “21. Revision Specific Behavior” on page 215.
122
Rev. 0.3