C8051F52X Datasheet, PDF (68/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
SFR Definition 7.1. REG0CN: Regulator Control
R/W
R/W
R
R/W
R
R
REGDIS Reserved — REG0MD —
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit7: REGDIS: Voltage Regulator Disable Bit.
This bit disables/enables the Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
Bit6: RESERVED. Read = 0b. Must write 0b.
Bit5: UNUSED. Read = 0b. Write = don’t care.
Bit4: REG0MD: Voltage Regulator Mode Select Bit.
This bit selects the Voltage Regulator output voltage.
0: Voltage Regulator output is 2.1 V.
1: Voltage Regulator output is 2.6 V (default).
Bits3–1: UNUSED. Read = 0b. Write = don’t care.
Bit0: DROPOUT: Voltage Regulator Dropout Indicator Bit.
0: Voltage Regulator is not in dropout.
1: Voltage Regulator is in or near dropout.
R
R
Reset Value
— DROPOUT 00010000
Bit1
Bit0
SFR Address: 0xC9
Table 7.1. Voltage Regulator Electrical Specifications
V_DD = 2.1 or 2.6 V; –40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min Typ
Input Voltage Range (V_REGIN)*
Dropout Voltage (V_DO)
Output Current = 1 mA
Output Current = 50 mA
2.7* —
TBD 10
TBD 500
Output Voltage (V_DD)
2.1 V operation (REG0MD = ‘0’)
2.6 V operation (REG0MD = ‘1’)
Output Current = 1 to 50 mA
TBD 2.1
TBD 2.6
—
—
Bias Current
2.1 V operation (REG0MD = ‘0’)
2.6 V operation (REG0MD = ‘1’)
—
1
—
1
Dropout Indicator Detection
Threshold
TBD —
Output Voltage Tempco
— 18
VREG Settling Time
50 mA load with V_REGIN = 2.4 V and
V_DD load capacitor of 4.8 µF
— 250
*Note: The minimum input voltage is 2.7 V or V_DD + V_DO(max load), whichever is greater.
Max
5.25
TBD
TBD
TBD
TBD
—
TBD
TBD
Units
V
mV
V
µA
TBD V
— mV/ºC
—
µs
68
Rev. 0.3