C8051F52X Datasheet, PDF (150/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 16.1. Timer Settings for Standard Baud Rates
Using the Internal Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
Frequency: 24.5 MHz
Baud Rate
% Error
Oscilla-
tor Divide
Factor
Timer Clock
Source
SCA1–SCA0
(pre-scale
select)*
Timer 1
T1M* Reload
Value (hex)
–0.32%
106
SYSCLK
XX
1
0xCB
–0.32%
212
SYSCLK
XX
1
0x96
0.15%
426
SYSCLK
XX
1
0x2B
–0.32%
848 SYSCLK / 4
01
0
0x96
0.15%
1704 SYSCLK / 12
00
0
0xB9
–0.32%
2544 SYSCLK / 12
00
0
0x96
–0.32%
10176 SYSCLK / 48
10
0
0x96
0.15%
20448 SYSCLK / 48
10
0
0x2B
X = Don’t care
*Note: SCA1–SCA0 and T1M bit definitions can be found in Section 19.1.
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Rev. 0.3