C8051F52X Datasheet, PDF(102/220 Page) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52X Datasheet, PDF (102/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52x-53x

SFR Definition 12.1. VDDMON: VDD Monitor Control

R/W

R

VDDMON VDDSTAT

Bit7

Bit6

R/W

VDMLVL

Bit5

R

R

R

R

R

Reset Value

Reserved Reserved Reserved Reserved Reserved 1v000000

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xFF

Bit7: VDDMON: VDD Monitor Enable.

This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets

until it is also selected as a reset source in register RSTSRC (SFR Definition 12.2). The VDD

Monitor can be allowed to stabilize before it is selected as a reset source. Selecting the

VDD monitor as a reset source before it has stabilized may generate a system reset.

See Table 12.1 for the minimum VDD Monitor turn-on time.

0: VDD Monitor Disabled.

1: VDD Monitor Enabled (default).

Bit6: VDDSTAT: VDD Status.

This bit indicates the current power supply status (VDD Monitor output).

0: VDD is at or below the VDD Monitor Threshold.

1: VDD is above the VDD Monitor Threshold.

Bit5: VDMLVL: VDD Level Select.

0: VDD Monitor Threshold is set to VRST-LOW (default).

1: VDD Monitor Threshold is set to VRST-HIGH. This setting is required for any system that

includes code that writes to and/or erases Flash.

Bits4â0: RESERVED. Read = Variable. Write = donât care.

12.3. External Reset

The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-

ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST

pin may be necessary to avoid erroneous noise-induced resets. See Table 12.1 for complete RST pin

specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.

12.4. Missing Clock Detector Reset

The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system

clock remains high or low for more than 100 Âµs, the one-shot will time out and generate a reset. After a

MCD reset, the MCDRSF flag (RSTSRC.2) will read â1â, signifying the MCD as the reset source; otherwise,

this bit reads â0â. Writing a â1â to the MCDRSF bit enables the Missing Clock Detector; writing a â0â disables

it. The state of the RST pin is unaffected by this reset.

12.5. Comparator Reset

Comparator0 can be configured as a reset source by writing a â1â to the C0RSEF flag (RSTSRC.5).

Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on

chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-

102

Rev. 0.3

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