C8051F52X Datasheet, PDF (169/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Access from application to data buffer and ID registers of the LIN core slave is possible when a data
request is pending (DTREQ bit in LINST register is ‘1’) and also when the LIN bus is not active (ACTIVE bit
in LINST register set to ‘0’).
The LIN peripheral in slave mode detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
An interrupt is requested after the reception of the IDENTIFIER FIELD, when an error is detected or when
the message transfer is completed.
The following steps have to be done by the application when an interrupt is requested.
1. Check the DTREQ bit in the status register (LINST) is set.(set when the IDENTIFIER FIELD
has been received). If set then:
2. Load the identifier from the LINID register and process it
3. Adjust the TXRX bit in the control register (LINCTRL) (set to “1” if the current frame is a trans-
mit operation for the slave and set to “0” if the current frame is a receive operation for the
slave)
4. Load the “data length” in the LINSIZE register (number of data bytes or value “1111b” if the
data length should be decoded from the identifier)
5. Load the data to transmit into the data buffer. (for transmit operation only)
6. Set the DTACK bit in the LINCTRL register.
Notes:
1. Steps 1a...1e have to be done during the IN-FRAME RESPONSE SPACE, if the current frame is a transmit
operation for the slave; otherwise a timeout will be detected by the master. If the current frame is a receive
operation for the slave, steps 1a...1e have to be finished until the reception of the first byte after the
IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN peripheral will be overwritten and a
timeout error will be detected in the LIN peripheral.
2. If the application detects an unknown identifier (e.g. extended identifier) it has to write a ‘1’ to the STOP bit
(LINCTRL) instead of setting the DTACK bit (steps 1b...1e can then be skipped). In that case the LIN peripheral
stops the processing of the LIN communication until the next SYNC BREAK is received.
3. Changing the setup of the checksum (classic to enhanced or vice versa) during a transaction will cause the
interface to reset and the transaction to be lost. Therefore no change in the checksum should be performed
while there is a transaction in progress.
4. The same applies to changes in the LIN interface mode from slave mode to master mode and from master
mode to slave mode.
5. Check the DONE bit in the status register if the DTREQ bit is not set. The transmission was successful if the
DONE bit is set.
6. If the transmission was successful and the current frame was a receive operation for the slave, load the
received data bytes from the data buffer. Else check the error register (LINERR) to determine the kind of error.
Further error handling has to be done by the application.
7. Set the RSTINT and RSTERR bits in the status register (LINCTRL) to reset the interrupt request and the error
flags.
Rev. 0.3
169