C8051F52X Datasheet, PDF (133/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
15. Oscillators
C8051F52x/53x devices include a programmable internal oscillator, an external oscillator drive circuit. The
internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as
shown in Figure 15.1. The system clock (SYSCLK) can be derived from the internal oscillator, external
oscillator circuit. Oscillator electrical specifications are given in Table 15.1 on page 142.
Option 2
VDD
XTAL2
Option 3
XTAL2
Option 1
XTAL1
10MΩ
XTAL2
Option 4
XTAL2
OSCICL
OSCICN
OSCIFIN
CLKSEL
EN
Programmable ^IOSC
Internal Clock
n
Generator
Input
Circuit
EXOSC
OSC
SYSCLK
OSCXCN
Figure 15.1. Oscillator Diagram
15.1. Programmable Internal Oscillator
All C8051F52x/53x devices include a programmable internal oscillator that defaults as the system clock
after a system reset. The internal oscillator period can be programmed via the OSCICL and OSCIFIN reg-
isters, shown in SFR Definition 15.2 and SFR Definition 15.3. On C8051F52x/53x devices, OSCICL and
OSCIFIN are factory calibrated to obtain a 24.5 MHz frequency.
Electrical specifications for the precision internal oscillator are given in Table 15.1 on page 142. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64,
or 128 as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
Rev. 0.3
133