C8051F52X Datasheet, PDF (152/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
The LIN peripheral is made of four major logic groups:
• LIN Interface Registers - Provide the interface between the microcontroller core and the peripheral.
• Data Buffer - Contains the registers where transmitted and received message data bytes are placed
• Registers Block - Contain all registers used to control the functionality of the interface
• Control State Machine and Bit Streaming Logic - Contains the hardware the serializes messages and
the timing control of the peripheral.
The LIN module does not directly support LIN Version 1.3 Extended Frames. In the case of a slave config-
uration if the application detects an extended frame it has to write a ‘1’ to the STOP bit (LINCTRL) instead
of setting the DTACK bit (steps 1b...1e can then be skipped). In that case the LIN peripheral stops the pro-
cessing of the LIN communication until the next SYNC BREAK is received.
17.2. Software Interface with the LIN Peripheral
The communication with the LIN interface is done indirectly through a pair of registers called LINADDR
and LINDATA and the Selection of the mode (Master or Slave) and the automatic baud rate feature are
done though the LINCF register. To write into a specific register other than these three ones require the
user to first load the LINADDR register with the address of the required LIN register and then load the data
to be transferred to the register using LINDATA.
In the following example the program reads the value of the LIN ERR Register into an auxiliary variable.
LINADDR = 0x0A;
//Address of LINERR
aux = LINDATA;
//Read content of LINERR into aux
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Rev. 0.3