C8051F52X Datasheet, PDF (61/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 5.2. ADC0 Electrical Characteristics (V_DD = 2.1 V, V_REF = 1.5 V)
V_DD = 2.1 V, V_REF = 1.5 V (REFSL = 0), –40 to +125 °C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
C8051F52x/C8051F53x
devices
—
—
±1
LSB
Differential Nonlinearity
Guaranteed Monotonic
—
—
±1
LSB
Offset Error
—
±1
—
LSB
Full Scale Error
—
±1
—
LSB
Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
C8051F52x/C8051F53x
devices
68
—
—
dB
Total Harmonic Distortion
Up to the 5^th harmonic
—
76
—
dB
Spurious-Free Dynamic Range
—
91
—
dB
Conversion Rate
SAR Conversion Clock
—
—
10
MHz
Conversion Time in SAR Clocks Note 1
—
13
—
clocks
Track/Hold Acquisition Time
Note 2
1
—
—
µs
Throughput Rate
—
—
200
ksps
Analog Inputs
Input Voltage Range
0
— 4.6 or 2.3 V
Input Capacitance
—
12
—
pF
Temperature Sensor
Linearity
Notes 3, 4
—
0.1
—
°C
Gain
Notes 3, 4
— 2.89
—
µV / °C
Offset
Notes 3, 4 (Temp = 0 °C)
— 888
—
mV
Power Specifications
Power Supply Current (V_DD sup- _{Operating Mode, 200 ksps}
— 840
—
µA
plied to ADC0)
Burst Mode (Idle)
— 880
—
µA
Power-On Time
TBD —
—
µs
Power Supply Rejection
— TBD
—
mV/V
Notes:
1. An additional 2 FCLK cycles are required to start and complete a conversion.
2. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “5.3.6. Settling Time Requirements” on page 48.
3. Represents one standard deviation from the mean.
4. Includes ADC offset, gain, and linearity variations.
Rev. 0.3
61