C8051F52X Datasheet, PDF (216/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
520
ANAB
628+
This character identifies
the Silicon Revision
Figure 21.3. Device Package - QFN 10
21.2. Reset Behavior
The reset behavior of C8051F52x and C8051F53x "REV A" devices is different than "REV B" and later
devices. The differences affect the state of the RST pin during a VDD Monitor reset.
On "REV A" devices, a V_DD Monitor reset does not affect the state of the RST pin. On "REV B" and later
devices, a V_DD Monitor reset will pull the RST pin low for the duration of the brownout condition.
21.3. UART Pins
The reset behavior of C8051F52x and C8051F53x "REV A" devices is different than "REV B" and later
devices. The location of the pins used by the serial UART interface is different between "REV A" and "REV
B" devices.
On "REV A" devices, the TX and RX pins used by the UART interface are mapped to the P0.3 (TX) and
P0.4 (RX) pins. On "REV B" and later devices, the TX and RX pins used by the UART interface are
mapped to the P0.4 (TX) and P0.5 (RX) pins.
21.4. LIN
The LIN peripheral behavior in "REV A" is different than the behavior of "REV B" and later devices. The
differences are:
21.4.1. Stop Bit Check
On "REV A" devices, the stop bits of the fields in the LIN frame are not checked and no error is generated
if the stop bits could not be sent or received correctly. On "REV B" and later devices, the stop bits are
checked, and an error will be generated if the stop bit was not sent or received correctly.
21.4.2. Synch Break and Synch Field Length Check
On "REV A" devices, the check of sync field length versus sync break length is incorrect. On "REV B" and
later devices, the sync break length must be larger than 10 bit times (of the measured bit time) to enable
the synchronization.
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Rev. 0.3