C8051F52X Datasheet, PDF (38/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Figure 4.2. QFN-20 Package Diagram
Table 4.5. QFN-20 Package Diagram Dimensions
Dimension
Min
Nom
Max
A
0.80
0.90
1.00
A1
0.03
0.07
0.11
A3
0.25 REF
b
0.18
0.25
0.30
D
4.00 BSC.
D2
2.55
2.70
2.85
e
0.50 BSC.
E
4.00 BSC.
E2
2.55
2.70
2.85
L
0.30
0.40
0.50
aaa
--
--
0.15
bbb
--
--
0.10
ddd
--
--
0.05
eee
--
--
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-43, variation VGGD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
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Rev. 0.3