C8051F52X Datasheet, PDF (120/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
P0
P1
SF Signals
TSSOP 20 and QFN 20
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NS S **
L I N-T X
LIN-RX
CP0
CP 0A
/ S YS CL K
CEX 0
CEX 1
CEX 2
ECI
T0
T1
0 1 2 3 4* 5* 6 7 0 1 2 3 4 5 6 7
00000001100 00000
P 0S KI P [0:7]
P1SKIP[0:7] = 0x 03
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
W hen these signals are enabled, the CrossB ar m ust be m anually configured
to skip their corresponding port pins.
*Note: Refer to Section “21. Revision Specific Behavior” on page 215.
**Note: 4-Wire SPI Only.
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped
(TSSOP 20 and QFN 20)
120
Rev. 0.3