C8051F52X Datasheet, PDF (195/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
19.2.3. External Capture Mode
Capture Mode allows either the external oscillator to be measured against the system clock. The external
oscillator clock can also be compared against each other. Timer 2 can be clocked from the system clock,
the system clock divided by 12, the external oscillator divided by 8, depending on the T2ML (CKCON.4),
T2XCLK, and T2RCLK settings. The timer will capture either every 8 eternal clock cycles, depending on
the T2RCLK setting. When a capture event is generated, the contents of Timer 2 (TMR2H:TMR2L) are
loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. By recording the
difference between two successive timer capture values, the external oscillator can be determined with
respect to the Timer 2 clock. The Timer 2 clock should be much faster than the capture clock to achieve an
accurate reading. Timer 2 should be in 16-bit auto-reload mode when using Capture Mode.
External Osc. / 8
SYSCLK / 12
T2XCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
SYSCLK
1
1
0
TR2
0
External Osc. / 8
TCLK
TMR2H
Capture
TMR2L
TMR2RLH TMR2RLL
TF2H
TF2L
TF2LEN
TF2CEN
TR2
TR2CLK
T2XCLK
Interrupt
TF2CEN
Figure 19.6. Timer 2 Capture Mode Block Diagram
Rev. 0.3
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