C8051F52X Datasheet, PDF(110/220 Page) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52X Datasheet, PDF (110/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52x-53x

13.2.1. VDD Maintenance and the VDD monitor

1. If the system power supply is subject to voltage or current "spikes," add sufficient transient

protection devices to the power supply to ensure that the supply voltages listed in the Absolute

Maximum Ratings table are not exceeded.

2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot

meet this rise time specification, then add an external VDD brownout circuit to the RST pin of

the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD

drops below 2.7 V.

3. Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code

as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-

based systems, this will involve modifying the startup code added by the 'C' compiler. See your

compiler documentation for more details. Make certain that there are no delays in software

between enabling the VDD monitor and enabling the VDD monitor as a reset source. Code

examples showing this can be found in âAN201: Writing to Flash from Firmware", available

from the Silicon Laboratories web site.

4. As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a

reset source inside the functions that write and erase Flash memory. The VDD monitor enable

instructions should be placed just after the instruction to set PSWE to a '1', but before the

Flash write or erase operation instruction.

5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment

operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-

ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.

6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas

to check are initialization code which enables other reset sources, such as the Missing Clock

Detector or Comparator, for example, and instructions which force a Software Reset. A global

search on "RSTSRC" can quickly verify this.

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