C8051F52X Datasheet, PDF (159/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
SFR Definition 17.14. LINERR: LIN ERROR Register
R
R
R
R
R
R
R
R
Reset Value
SYNCH PRTY TOUT
CHK BITERR 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
0x0A
(indirect)
Bit7–5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 000b. Write = don’t care.
SYNCH: Synchronization Error bit.(slave mode only)
The peripheral detected edges of the SYNCH FIELD outside the maximum tolerance.
PRTY: Parity Error bit.(slave mode only)
This bit is set when a parity error is detected.
TOUT: Timeout Error Bit.
This bit is set whenever one of the following conditions is met:
1- The master detects a timeout error if it is expecting data from the bus but no slave does
respond.
2- If the slave responds to late and the frame is not finished within the maximum frame
length T_{FRAME_MAX}.
3- The slave detects a timeout error if it is expecting data from the master or another slave
but no data is transmitted on the bus.
4- If the frame is not finished within the maximum frame length T^FRAME_MAX is reached.
5- The slave detects a timeout error if it is requesting a data acknowledge to the application
(for selecting receive or transmit, data length and loading data) and the application does not
set the DTACK bit (LINCTRL) or STOP bit (LINCTRL) until the end of the reception of the
first byte after the identifier.
6- The slave detects a timeout error if it has transmitted a wakeup signal and it detects no
sync field (from the master) within 150 ms.
CHK: Checksum Error Bit.
The bit is set when the peripheral detects a checksum error.
BITERR: Bit Error bit.
This error bit is set when the bit value monitored by the peripheral is different from the one
sent.
Rev. 0.3
159