C8051F52X Datasheet, PDF (164/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 17.3. Manual Bit-Rate Parameters Examples
Baud
20 K
19.2 K
9.6 K
4.8 K
1K
(bits/sec)
SYSCLK
(MHz)
25
24.5
24
22.1184
16
12.25
12
11.0592
8
0 1 312 0 1 325 1 1 325 3 1 325 19 1 312
0 1 306 0 1 319 1 1 319 3 1 319 19 1 306
0 1 300 0 1 312 1 1 312 3 1 312 19 1 300
0 1 276 0 1 288 1 1 288 3 1 288 19 1 276
0 1 200 0 1 208 1 1 208 3 1 208 19 1 200
0 0 306 0 0 319 1 0 319 3 0 319 19 0 306
0 0 300 0 0 312 1 0 312 3 0 312 19 0 300
0 0 276 0 0 288 1 0 288 3 0 288 19 0 276
0 0 200 0 0 208 1 0 208 3 0 208 19 0 200
17.4.4. Baud Rate Calculations - Automatic Mode
The designer may choose to use the automatic bit rate feature of the Slave Peripheral. In this case only the
prescaler and divider must be calculated as follows:
prescaler = ln ^S----^Y----^S---^C----^L----^K-- × ---1---- – 1
4000000 ln2
divider = _2----(--_p--_r--_e--_s--_c--^S-_a--_l-^Y-_e--_r^S---₊-^C--₁--^L-₎---^K_×-----2---0---0---0---0-
In the following example it is calculated the value of these factors for a system clock (SYSCLK) of
24.5 MHz:
prescaler = ln ^{2----4---5---0--0---0----0---0-} × ---1---- – 1 = 1.615 ≅ 1
4000000 ln2
divider
=
-------2---4---5---0---0---0---0---0--------
2^{(1 + 1)} × 20000
=
306.25 ≅ 306
Table 17.4 presents some typical values of system clock and bit rate along with their factors.
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