C8051F52X Datasheet, PDF (174/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Master
Device 1
NSS
MISO
MOSI
SCK
GPIO
GPIO
MISO
MOSI
SCK
NSS
Master
Device 2
Figure 18.2. Multiple-Master Mode Connection Diagram
Master
Device MISO
MOSI
SCK
Slave
MISO Device
MOSI
SCK
Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram
Master
Device
GPIO
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
NSS
Slave
Device
MISO
MOSI
SCK
NSS
Slave
Device
Figure 18.4. 4-Wire Single Master and Slave Mode Connection Diagram
18.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted into the shift register,
the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive
buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master
device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered,
and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer
will immediately be transferred into the shift register. When the shift register already contains data, the SPI
will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current)
SPI transfer.
174
Rev. 0.3