C8051F52X Datasheet, PDF (26/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
1.5. Programmable Comparator
C8051F52x/F53x devices include a software-configurable voltage comparator with an input multiplexer.
The comparator offers programmable response time and hysteresis and an output that is optionally avail-
able at the Port pins: a synchronous “latched” output (CP0). The comparator interrupt may be generated
on rising, falling, or both edges. When in IDLE or SUSPEND mode, these interrupts may be used as a
“wake-up” source for the processor. The Comparator may also be configured as a reset source. A block
diagram of the comparator is shown in Figure 1.6.
Port I/O
Pins
VDD
Interrupt
Logic
+
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
Reset
Decision
Tree
CP0
(synchronous output)
CP0A
(asynchronous output)
Figure 1.6. Comparator Block Diagram
1.6. Voltage Regulator
C8051F52x/F53x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at
the V_REGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 or 2.6 V. When
enabled, the output of REG0 powers the device and drives the V_DD pin. The voltage regulator can be used
to power external devices connected to V_DD.
1.7. Serial Port
The C8051F52x/F53x Family includes a full-duplex UART with enhanced baud rate configuration, and an
Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
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Rev. 0.3