C8051F52X Datasheet, PDF (31/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

4. Pinout and Package Definitions
C8051F52x-53x
RST/C2CK 1
P0.0/V_REF 2
GND 3
V_DD 4
V_REGIN 5
C8051F520/1/3/4/6/7
Top View
GND
10 P0.1/C2D
9 P0.2/XTAL1
8 P0.3/XTAL2
7 P0.4/TX
6 P0.5/CNVSTR/RX
Name
RST/
C2CK
P0.0/
V_REF
Table 4.1. Pin Definitions for the C8051F520 (QFN 10)
Pin
Type Description
D I/O _{Device Reset. Open-drain output of internal POR or VDD monitor. An}
external source can initiate a system reset by driving this pin low for at
1
least 15 µs. A 1 kΩ pullup to V_DD is recommended. See Reset
Sources Section for a complete description.
D I/O _{Clock signal for the C2 Debug Interface.}
D I/O or _{Port 0.0. See Port I/O Section for a complete description.}
A In
2
A O or
D In
External V_REF Input. See V_REF Section.
GND
V_DD
V_REGIN
P0.5/RX*/
CNVSTR
P0.4/TX*
3
Ground.
4
Core Supply Voltage.
5
On-Chip Voltage Regulator Input.
D I/O or _{Port 0.5. See Port I/O Section for a complete description.}
A In
6
D In External Converter start input for the ADC0, see Section “5. 12-Bit
ADC (ADC0)” on page 41 for a complete description.
7
D I/O or _{Port 0.4. See Port I/O Section for a complete description.}
A In
*Note: Please refer to Section “21. Revision Specific Behavior” on page 215.
Rev. 0.3
31