C8051F52X Datasheet, PDF (33/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
P0.2 1
P0.1 2
RST/C2CK 3
P0.0/V_REF 4
GND 5
V_DD 6
V_REGIN
7
P1.7 ⁸
P1.6 ⁹
P1.5 ¹⁰
20 P0.3
19 P0.4/TX
18 P0.5/RX
17 P0.6/C2D
16 P0.7/XTAL1
15 P1.0/XTAL2
14 _P1.1
13 _P1.2/CNVSTR
12 _P1.3
11 _P1.4
Table 4.2. Pin Definitions for the C8051F530 (TSSOP 20)
Name
P0.2
P0.1
RST/
Pin
Type Description
1
D I/O or _{Port 0.2. See Port I/O Section for a complete description.}
A In
2
D I/O or _{Port 0.1. See Port I/O Section for a complete description.}
A In
D I/O _{Device Reset. Open-drain output of internal POR or VDD monitor. An}
external source can initiate a system reset by driving this pin low for at
3
least 15 µs. A 1 kΩ pullup to V_DD is recommended. See Reset
Sources Section for a complete description.
C2CK
P0.0/
V_REF
D I/O _{Clock signal for the C2 Debug Interface.}
D I/O or _{Port 0.0. See Port I/O Section for a complete description.}
A In
4
A O or
D In
External V_REF Input. See V_REF Section.
GND
5
Ground.
V_DD
V_REGIN
P1.7
6
Core Supply Voltage.
7
On-Chip Voltage Regulator Input.
8
D I/O or _{Port 1.7. See Port I/O Section for a complete description.}
A In
P1.6
9
D I/O or _{Port 1.6. See Port I/O Section for a complete description.}
A In
*Note: Please refer to Section “21. Revision Specific Behavior” on page 215.
Rev. 0.3
33