C8051F52X Datasheet, PDF (79/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 9.1. CIP-51 Instruction Set Summary¹ (Continued)
Mnemonic
Description
Boolean Manipulation
Bytes
Clock
Cycles
CLR C
CLR bit
SETB C
Clear Carry
Clear direct bit
Set Carry
1
1
2
2
1
1
SETB bit
Set direct bit
2
2
CPL C
CPL bit
ANL C, bit
Complement Carry
Complement direct bit
AND direct bit to Carry
1
1
2
2
2
2
ANL C, /bit
AND complement of direct bit to Carry
2
2
ORL C, bit
ORL C, /bit
MOV C, bit
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
2
2
2
2
2
2
MOV bit, C
Move Carry to direct bit
2
2
JC rel
JNC rel
JB bit, rel
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
2
2/4
2
2/4
3
3/5
JNB bit, rel
Jump if direct bit is not set
3
3/5
JBC bit, rel
ACALL addr11
Jump if direct bit is set and clear bit
Program Branching
Absolute subroutine call
3
3/5
2
4
LCALL addr16
Long subroutine call
3
5
RET
RETI
AJMP addr11
Return from subroutine
Return from interrupt
Absolute jump
1
6
1
6
2
4
LJMP addr16
Long jump
3
5
SJMP rel
JMP @A+DPTR
JZ rel
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
2
4
1
4
2
2/4
JNZ rel
Jump if A does not equal zero
2
2/4
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
3
3/5
3
3/5
3
3/5
3
4/6
DJNZ Rn, rel
DJNZ direct, rel
NOP
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
2/4
3
3/5
1
1
Notes:
1. Assumes PFEN = 1 for all instruction timing.
2. MOVC instructions take 4 to 7 clock cycles depending on instruction alignment and the FLRT setting.
Rev. 0.3
79