C8051F52X Datasheet, PDF (100/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
12.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V_DD settles above
V_RST. An additional delay occurs before the device is released from reset; the delay decreases as the V_DD
ramp time increases (V_DD ramp time is defined as how fast V_DD ramps from 0 V to V_RST). Figure 12.2 plots
the power-on and V_DD monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
delay (T_PORDelay) is typically less than 0.3 ms.
Note: The maximum V_DD ramp time is 1 ms; slower ramp times may cause the device to be released from
reset before V_DD reaches the V_RST level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V_DD monitor is enabled following
a power-on reset.
V_RST
1.0
VDD
t
Logic HIGH ^/RST
Logic LOW
T _{P O R D e la y}
P ow er-O n
Reset
VDD
M o n ito r
Reset
Figure 12.2. Power-On and V_DD Monitor Reset Timing
100
Rev. 0.3