C8051F52X Datasheet, PDF (183/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 18.1. SPI Slave Timing Parameters
Parameter
Description
Min
Master Mode Timing* (See Figure 18.6 and Figure 18.7)
T_MCKH
SCK High Time
1 x T_SYSCLK
T_MCKL
SCK Low Time
1 x T_SYSCLK
T_MIS
MISO Valid to SCK Sample Edge
20
T_MIH
SCK Sample Edge to MISO Change
0
Slave Mode Timing* (See Figure 18.8 and Figure 18.9)
T_SE
T_SD
T_SEZ
T_SDZ
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
2 x T_SYSCLK
2 x T_SYSCLK
—
—
T_CKH
T_CKL
T_SIS
T_SIH
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
T_SOH
SCK Shift Edge to MISO Change
—
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK) in ns.
The maximum possible frequency of the SPI can be calculated as:
Transmission: SYSCLK/2
Reception: SYSCLK/10
Max
Units
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
Rev. 0.3
183