C8051F52X Datasheet, PDF (44/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Convert Start
Pre-Tracking
AD0TM = 10
Post-Tracking
AD0TM= 01
Dual-Tracking
AD0TM = 11
Track
Idle
Track
Convert
Track
Convert
Track
Convert
Track
Convert ...
Idle
Track Convert..
Track
Track Convert..
Figure 5.3. ADC0 Tracking Modes
5.3.3. Timing
ADC0 has a maximum conversion speed specified in Table 5.1 and Table 5.2. ADC0 is clocked from the
ADC0 Subsystem Clock (FCLK). The source of FCLK is selected based on the BURSTEN bit. When
BURSTEN is logic 0, FCLK is derived from the current system clock. When BURSTEN is logic 1, FCLK is
derived from the Burst Mode Oscillator, an independent clock source with a maximum frequency of
25 MHz.
When ADC0 is performing a conversion, it requires a clock source that is typically slower than FCLK. The
ADC0 SAR conversion clock (SAR clock) is a divided version of FCLK. The divide ratio can be configured
using the AD0SC bits in the ADC0CF register. The maximum SAR clock frequency is listed in Table 5.1
and Table 5.2.
ADC0 can be in one of three states at any given time: tracking, converting, or idle. Tracking time depends
on the tracking mode selected. For Pre-Tracking Mode, tracking is managed by software and ADC0 starts
conversions immediately following the convert start signal. For Post-Tracking and Dual-Tracking Modes,
the tracking time after the convert start signal is equal to the value determined by the AD0TK bits plus 2
FCLK cycles. Tracking is immediately followed by a conversion. The ADC0 conversion time is always 13
SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion. Figure 5.4 shows
timing diagrams for a conversion in Pre-Tracking Mode and tracking plus conversion in Post-Tracking or
Dual-Tracking Mode. In this example, repeat count is set to one.
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