C8051F52X Datasheet, PDF (88/220 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x-53x
Table 10.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address
Description
ACC
0xE0
Accumulator
ADC0CF
0xBC
ADC0 Configuration
ADC0CN
0xE8
ADC0 Control
ADC0H
0xBE
ADC0
ADC0L
0xBD
ADC0
ADC0GTH
0xC4
ADC0 Greater-Than Data High Byte
ADC0GTL
0xC3
ADC0 Greater-Than Data Low Byte
ADC0LTH
0xC6
ADC0 Less-Than Data High Byte
ADC0LTL
0xC5
ADC0 Less-Than Data Low Byte
ADC0MX
0xBB
ADC0 Channel Select
ADC0TK
0xBA
ADC0 Tracking Mode Select
B
0xF0
B Register
CKCON
0x8E
Clock Control
CLKSEL
0xA9
Clock Select
CPT0CN
0x9B
Comparator0 Control
CPT0MD
0x9D
Comparator0 Mode Selection
CPT0MX
0x9F
Comparator0 MUX Selection
DPH
0x83
Data Pointer High
DPL
0x82
Data Pointer Low
EIE1
0xE6
Extended Interrupt Enable 1
EIP1
0xF6
Extended Interrupt Priority 1
FLKEY
0xB7
Flash Lock and Key
IE
0xA8
Interrupt Enable
IP
0xB8
Interrupt Priority
IT01CF
0xE4
INT0/INT1 Configuration
LINADDR
0x92
LIN indirect address pointer
LINCF
0x95
LIN master-slave and automatic baud rate selection
LINDATA
0x93
LIN indirect data buffer
OSCICL
0xB3
Internal Oscillator Calibration
OSCICN
0xB2
Internal Oscillator Control
OSCXCN
0xB1
External Oscillator Control
P0
0x80
Port 0 Latch
P0MASK
0xC7
Port 0 Mask
P0MAT
0xD7
Port 0 Match
P0MDIN
0xF1
Port 0 Input Mode Configuration
P0MDOUT
0xA4
Port 0 Output Mode Configuration
P0SKIP
0xD4
Port 0 Skip
P1
0x90
Port 1 Latch
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