HD64336900G Datasheet, PDF (79/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

3.2.6 Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 interrupt requests.
Initial
Bit
Bit Name Value
7

0
6


5
IRRTB1 0
4 to 0 
All 1
R/W Description

Reserved
This bit is always read as 0.

Reserved
R/W Timer B1 Interrupt Request Flag
[Setting condition]
When timer B1 overflows
[Clearing condition]
When IRRTB1 is cleared by writing 0

Reserved
These bits are always read as 1.
3.2.7 Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7, 6 
All 1

Reserved
These bits are always read as 1.
5
IWPF5 0
R/W WKP5 Interrupt Request Flag
[Setting condition]
When WKP5 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0
4 to 0 
All 0

Reserved
These bits are always read as 0.
Rev. 1.00, 11/03, page 51 of 376