HD64336900G Datasheet, PDF (287/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Initial
Bit
Bit Name Value R/W Description
3
CKS
0
R/W Clock Select
Selects the A/D conversions time
0: Conversion time = 134 states (max.)
1: Conversion time = 70 states (max.)
Clear the ADST bit to 0 before switching the conversion
time.
2
CH2
0
R/W Channel Select 0 to 2
1
CH1
0
R/W Select analog input channels.
0
CH0
0
R/W When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 to AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
Note: When executing the A/D conversion through AN3
or AN2, do not set the VDDII bit in LVDCR to 0. If 0
is set, the A/D conversion accuracy is not
guaranteed.
16.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Initial
Bit
Bit Name Value R/W Description
7
TRGE
0
R/W Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit
is set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
6 to 4 —
All 1
—
Reserved
These bits are always read as 1.
3, 2 —
All 0
R/W Reserved
Although these bits are readable/writable, they should not
be set to 1.
Rev. 1.00, 11/03, page 259 of 376