HD64336900G Datasheet, PDF (209/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
WDT dedicated
internal oscillator
CLK
PSS
TCSRWD
TCWD
TMWD
[Legend]
TCSRWD: Timer control/status register WD
TCWD: Timer counter WD
PSS:
Prescaler S
TMWD: Timer mode register WD
Internal reset
signal
Figure 13.1 Block Diagram of Watchdog Timer
13.1 Features
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the
WDT dedicated internal oscillator can be selected as the timer-counter clock. When the WDT
dedicated internal oscillator is selected, it can operate as the watchdog timer in any operating
mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• The watchdog timer is enabled in the initial state.
It starts operating after the reset state is canceled.
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Rev. 1.00, 11/03, page 181 of 376